A costly technique for using two masks to produce one semiconductor wafer etching at the 22 nm level may be minimized, thanks to a process that IBM announced today, though for obvious reasons has not completely explained.

The need for devices to reduce power consumption is the chief motivator behind the drive to shrink the size of components. It's not like we need more space anymore; smaller components are simply, by design, more efficient. But it takes a tremendous array of new efficiencies along the way to yield that power efficiency at the end, and one of the problems facing chip manufacturers has been, how to implement these new processes without completely overhauling factories.

This afternoon, IBM announced it has come up with a methodology that's a blend of applied mathematics, virtual modeling, and old-world lithography techniques, to minimize the impact of one of the biggest changes factories -- including IBM's own -- will have to face. New components -- especially NAND flash memory for embedded devices and memory cards -- need 22 nm lithography as soon as it's possibly available.

But it's not easy to simply shrink the masks needed to guide the light used to steer the circuit patterns, in proportion with the lithographic scale. When you scale optical masks down in size past a certain point, the likelihood that they'll lead to errors in the lithography process jumps dramatically. For modern lithographic processes to work at the 22 nm level, engineers found they actually need to use more than one mask, for a process known as double patterning. Imagine shining a light against a bed sheet, and blocking the light source with two masks instead of just one, and you'll get the basic principle.

One double patterning process actively being considered just this last spring involved using a thermal trick to imprint an image from one mask, literally freeze it in place, and then imprint an image from a second mask before the etch begins -- a process given the highly technical term litho-freeze-litho-etch. But the problem with that process, even with the 32 nm scale to which IBM is already transitioning, is that the error allowance rates have to be cut in half for each mask, in order to maintain the same tolerance levels.

That requires a tremendous degree of process optimization, and here is where IBM's mathematics enters the picture.

IBM has an entire division dedicated to the problem of computational scaling, which is the application of simple laws governing how any system can be scaled up or down, and at what point scaling to any extreme leads to diminishing or negative returns. Applied to a virtual model of chip fabrication, computational scaling models can determine the extent to which double patterning actually needs to be used at all with certain types of designs.

So the news today is IBM's development of a process of source mask optimization (actually not a new concept -- IBM has patents on it dating back to at least 1995) that could lead to a much more viable compromise for chip producers. They'll implement new photomask fabrication techniques, to be certain, enabling higher resolution through a process developed through virtual fabrication testing. But they'll also conceivably utilize double patterning less often than earlier feared, because the masks themselves will be more highly optimized.

This doesn't mean 22 nm fabrication will start tomorrow. However, IBM made clear today, it intends to use this process to build better semiconductors "for cloud computing, laptops, game consoles, and cell phones." That #3 item in the list is a veiled reference to the Cell BE processor, the heart of Sony's PlayStation 3 and the chip whose IP is now majority-owned by IBM. Source mask optimization could very well be the development that spells the dawn of the "PS4."