The term "latecomer" is a particularly uncomfortable one for AMD. So for its 45 nm CPU unveiling at CeBIT in Hannover today, the company had to make the case that, despite being later, Shanghai and Deneb will be technologically better.

It's now an unavoidable asterisk in AMD's history: Intel introduced its first 45 nm CPUs to consumers last fall. So the fanfare accompanying the demonstration of AMD's first 45 nm quad-core CPUs just today at CeBIT in Hannover can't come from the usual source. It's following up, and it has to catch up fast, but it won't have the full arsenal of process technologies that Intel is already putting to use.

Fab 36 in Dresden, AMD announced today, has gone to work to produce the first models, which an AMD spokesperson told BetaNews will go to select customers for testing. The process technology co-developed with IBM, to which AMD referred in its announcement this morning, is the extreme ultra-violet lithography process announced last week. It is not, as some had hoped, the high-k+metal gate (HK+MG) process that AMD and IBM raced to discover, and that Intel is already implementing.

"We have high-k+metal gate as an option at 45 nm; we haven't announced any products that will use high-k+metal gate," spokesperson Gary Silcott told us. "It will come later on in our 45 nm process, so our initial 45 nm process does not include that."

At this time, AMD doesn't see HK+MG as a priority, Silcott said, because it has yet to demonstrate the same degree of performance improvement for AMD's lithography as it does for Intel's.

One of the key differentiators between AMD and Intel process technology continues to be their choice of substrates. Years ago, Intel made a conscious choice to stick with ordinary CMOS, or "bulk silicon," while AMD introduced an insulating layer in its base wafer, for what's called silicon-on-insulator (SOI). That reduced power leakage considerably already, which is one of the key benefits of HK+MG.

But that benefit is best appreciated for a bulk silicon substrate, which arguably needs it most, Silcott remarked. "Because we use silicon-on-insulator substrates as opposed to bulk silicon that Intel uses," he said, "SOI gives us a certain amount of advantages at a performance-per-watt level...as well as other things that we do in terms of our design and our process. [So] we don't feel like we're going to be lacking by not having high-k+metal gate right away."

Intel has claimed it made the choice to stick with bulk silicon because SOI doesn't scale as well at smaller lithography levels, it's too costly to implement for the benefits it produces, and that it actually introduces a problem at smaller scales: With a CPU's SOI supporting a higher thermal resistance, it requires a higher operating temperature, according to Intel's explanation. Typically that implies higher power consumption.

But AMD's Silcott believes that a dielectric advancement at the opposite end of the picture -- ultra-low-k interconnect dielectrics -- will help make up the gap due to the lack of a high-k advancement at the gate level.

"Ultra-low-k interconnect dielectrics [will] also bring us some power consumption savings," Silcott told BetaNews. "So if you take it all as a whole, and look at the design and our process, we feel like we're sitting fine without introducing high-k+metal gate at our first 45 nm process. 45 nm is going to have a few years of lifetime, of course, and we'll take a look at it in the future [with regard to] whether or not we bring it in."

AMD's code names for its first 45 nm generations are "Shanghai" for server processors and "Deneb" for its enthusiast quad-core line. These will be the first two market segments to see 45 nm, though Silcott said it's too soon to say which line AMD may release first, or whether they'll be released together.

The process roadmap for AMD at this point remains uncharacteristically wide, with Silcott maintaining that general purpose release remains slated for the second half of this year -- which is coming up awfully soon. He also kept a tight lid on any mention of performance projections.

However, Silcott did point us to one key improvement which could shed some light as to what we can expect, performance-wise, in at least one department: "One of the things that distinguishes Shanghai from its predecessor, which was Barcelona, is the 6 MB of Level 3 cache that's on that product. Being able to put that 6 MB of Level 3 cache on there is definitely correlated to moving to the 45 nm process, because of the transistor budget that you get from scaling."

Previous tests of similar performance boosts for previous processors and prototypes, discovered in BetaNews' research, turned up as much as 15% performance improvement attained just on account of the bigger cache alone. The only Intel processors to benefit from L3 are the higher-order Xeons, which pool together between 4 MB for the 95 W models and 16 MB for the 150 W models.

Silcott went on to say AMD's 32 nm generation will be ready for public consumption no sooner than early 2010, and possibly into 2011.