IBM to Announce Breakthrough Caching Innovation at ISSCC
This morning, IBM confirmed to BetaNews that later this afternoon, its engineers are scheduled to demonstrate their own concept chip, which will utilize an embedded memory architecture for caching. The company is saying it could double the performance of existing 65 nm processors and future generations by tripling its cache memory capacity and perhaps increase the throughput of that memory tenfold.
The demonstration will take place at the International Solid-State Circuits Conference, where on Monday Intel demonstrated its own concept chip, whose architecture is based on the fabricator’s ability to stamp out multiple cores side-by-side as tiles. IBM’s counter-argument today may very well prove that core multiplication may not be the most efficient way to achieve performance gains.
Once again, the best clues for exactly what IBM will be demonstrating, prior to the announcement itself, come from the ISSCC session agenda. This conference is attended by professional engineers, upon whom the typical hyperboles and poetically crafted adjectives embellishing the benefits of power and performance typically fall flat. If they’re going to spend one hour of their lives in a session with IBM, they need to know what it’s truly about first.
So this paragraph sets the stage: “A prototype SOI embedded DRAM macro is developed for high-performance microprocessors and introduces a performance-enhancing 3T [three-transistor cell] micro sense amplifier architecture (mSA). The macro was characterized via a test chip fabricated in a 65nm SOI deep-trench DRAM process. Measurements confirm 1.5ns random access time with a 1V supply at 85°C and low voltage operation with a 600mV supply.”
What are they talking about? Here, the technology is actually simpler than it sounds: A sense amplifier literally performs the function of a amplifier in a sound system, boosting the voltage of signals traveling along the internal lines of the chip. When you pile more and more components onto a chip – as appears to be the current trend – the opportunities for signal degradation increase.
Hitachi may be credited for having attacked this problem first in 2001, and having realized that sense amplifiers could hold the key to a solution. The problem Hitachi was trying to solve back then was to find a way to increase the real estate on chips for cache memory, as a way of reducing the need for more and more DRAM on a circuit board or motherboard, which typically accounts for 20% of a system’s power consumption. Less DRAM and more cache could mean less power wasted. So Hitachi developed a technique where sense amplifiers could be deployed inline, to compensate for the fact that boosting on-board cache would increase the number of components on the chip, and perhaps degrade the signals coming from SDRAM.
IBM is taking this concept a few steps further, applying it to the innermost SRAM of a CPU. One of the most recognized problems in system design by engineers is the fact that logic components’ performance are rising much faster than that of memory components. As a result, much of the performance capability of existing processor designs might not even be realized, due to the broadening timing gaps between logic and memory.
Typical SRAM access time today hovers around 5 ns. This is a problem, especially with 3 GHz processors whose access time, by definition, should be 3 ns; and the problem is compounded by multiple cores. Techniques such as the HyperTransport memory bus between cores, used by AMD, alleviate contention problems; but theoretically, the best that HyperTransport could possibly do is restore the timing gap to this 3:5 ratio, which in practical use means requests from CPU cores for memory continue to wait on a queue.
IBM, in its abstract presented to ISSCC, claims a 1.5 ns access time for embedded RAM (which typically includes SRAM), for its concept chip with the micro-miniaturized sense amplifiers. If these statistics are sustained independently, the cache memory gap may be completely sealed; and unless clock cycles for CPUs resume their previous state of incline, that seal could hold for several years.
As a bonus, signal amplification translates to lower power leakage. And with the model chip having been built using 65 nm, the chances increase for both IBM and its technology partner AMD to deploy mSA architecture within a near-term timeframe - conceivably 18 months, though IBM and AMD have yet to confirm that speculation.
