RSSIntel Officially Confirms Integrated Memory Controller for 45nm Nehalem
By Scott M. Fulton, III | Published March 28, 2007, 8:15 PM
This afternoon, Intel confirmed to BetaNews what its executive vice president, Pat Gelsinger, inadvertently revealed in comments to reporters several weeks ago, and what the Wall Street Journal learned this morning after having read The Register from several days ago: Intel's second generation of 45nm CPU architecture, code-named "Nehalem," will integrate memory controllers typically featured in the northbridge component of Intel chipsets, into the CPU itself.
Actually, knowledgeable sources came to the conclusion that Intel must be integrating its memory controller into the CPU based on information received as early as last July. TG Daily carefully glanced over the possibility at that time, before raising speculation the following September: Intel's comments to that time about something it calls scalable cache sizes led to no other conclusion. How could a chipset possibly scale the cache of something residing off the main memory bus?
The publication raised the question directly with Intel again last February. But surprisingly, an Intel spokesperson downplayed the rumors by effectively confirming that Intel would not integrate memory controllers into its Penryn CPUs -- the first generation of 45nm architecture. Intel then went on to explain why such integration may be a bad design choice, using AMD -- which has used integrated HyperTransport since before the dual-core era - as a negative example.
In an amended fact sheet today, Intel states integrated memory controllers will be a Nehalem feature when that new microarchitecture begins production in 2008. It also has added a curious new characterization: "simultaneous multi-threading," which it now states is similar to hyperthreading.
HT technology was introduced in 2005 as a kind of stopgap measure prior to the introduction of dual-core processors - an introduction many believed to have been substantively expedited by AMD. Previously, Intel effectively confirmed to multiple press sources that it would be using HT in Nehalem, though this re-characterization appears to have borrowed the same cloud that once hung over the northbridge, to fuzzify the issue of on-board parallelism.
Never a company to let an opportunity for uncertainty over its rival go to waste, AMD weighed in this afternoon in a comment to BetaNews: "Our competitor's announcement today is further validation that [Intel's] current architecture will not be competitive with Barcelona [AMD's forthcoming 65nm CPUs later this year] until they make this transition that we showed the industry in 2003 with Direct Connect Architecture," remarked AMD corporate VP Randy Allen.
"The dual-core performance leadership we have today is building a bridge to Barcelona and the increased performance it will deliver in a non-disruptive fashion. We are not requiring our customers to make wholesale infrastructure changes in order to achieve incremental performance gains."
I think most forget that Intel dropped two p4 core revisions to bring out core2duo to get ahead of AMD and to have a decent quad core(can u imagine quad core net bust)
Core2duo was to fight AMD "Barcelona" before Intel change its chip time line
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|AMD = dead
INTEL = ownz your mom
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|You must be confused. Intel here is going back on their word of not including a memory controller on the chip. AMD has had this since 2003. I'd say that the new product AMD produces won't by any means be something intel can just flip a few switches and be on top again. Core 2 Duo was catch up. they did a great job to beat older archicture. Once the .65nm and then the .45nm chips come out, we will see some good things come out of all chips.
This competitive nature they are having is pushing the envelope for all uses, not just gamers or server farms...It is neither AMD nor Intel that are the winners; we are those winners.
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|Maybe, maybe not...but this is pointing out that AMD led the way at least.
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|Guess Intel finally realized that it makes little sense to rely soley upon your home-grown technology advantage when you can combine it with someone else's. The customer could care less about who developed what first: its all about the price-to-performance ratio. A few years from now I suspect you'll need special glasses to tell an AMD chip from an Intel one.
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|Hyperthreading is beneficial on a dual core or more system too, its just harder to implement. The fact that it did (supposedly) have a 10 percent gain in performance is a good thing. On a single core chip its in relative terms, simple to have the multithreading logic. There's two 'equal virtual processors' so in the grand scheme of things it doesn't matter which virtual processor the thread is executed in.
When you have a dual core multithreaded system you have two real processors and two virtual processors. The problem implementing hyperthreading is in the core logic of the chip, which has to decide whether each thread should be executed in a 'real processor' alone or whether it should be executed in one of the four 'virtual processors'. The real processors in this instance has the two virtual processors in it. Don't know if that makes any sense but...
They could just from the software level still have it as a single/multithreading app, and on a processor level just direct the thread to the virtual processor with the least load...
My point is anyway, the main reason why it wasn't included in Conroe etc to start with would be difficulty in implementation. To say it was because it wasn't seen as necessary is a bit of bull, since it would sound quite intrigueing having the ability to run 4 threads simultaneously.
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|AMD and Intel have been licensing tech from each other for a long time - this is nothing new. I don't think we need to worry about their competitiveness in the future. There will still be plenty to differentiate the two - after all, they still use completely different manufacturing principles.
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|Hyperthreading was just a desperate attempt by Intel to beat AMD to the punch with a processor that can run multiple threads simultaneously. Thankfully it failed miserably. There is no significant performance gain from hyperthreading. It doesn't matter if you are doing something like audio/video encoding or running a high end scientific application. The only way to get a significant performance boost is to add more real cores.
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|A few years from now I suspect you'll need special glasses to tell an AMD chip from an Intel one.
Actually, the way Intel have been talking about massively multi-core chips and AMD have been talking about specialized heterogeneous multiprocessing, I wouldn't be surprised if they start diverging even further from each other. (Of course, once they do, the company happening to fall behind will probably change its course anyway.)
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|apparently you dont know too much about HT, nor have you used a program that took advantage of it.
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|Actually HyperThreading-like technology was used by IBM and Sun long time before Intel included it in its CPUs. Sun implementations allow for 4-threads per physical core...
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|Why do I get the feeling that Scot thinks that HyperTransport, HyperThreading and integrated memory controllers are all the same thing?
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|You don't expect news to be accurate here do you? When did that ever matter here? Post anything you like, leave it for a week, make a subtle change, and pretent it never happened is the usual course here..
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|Well, Tene, that's probably because you're acting out of your feelings rather than your knowledge. If you're an intelligent reader - and I'd like to think you are - you know full well I know the difference between memory bus control and parallelism. In fact, I am quite seriously working on a plan in which the vital concepts you describe are explained here, in excruciating detail, right here in BetaNews. And if not by me, then by one of our other equally knowledgeable editors.
Your confusion arises from the fact that HyperTransport and hyperthreading have the same initials. Intel has in the past referred to the latter as "HTT" with respect to its own implementation; however, please note it no longer does so:
http://www.intel.com/pro...hyperthreading_more.htm
I had produced a number of more scientific articles explaining these technologies for Tom's Hardware Guide, but sadly, these appear to have been taken down in the last site redesign.
With regard to the other reply to your comment, I think knowledgeable readers know full well that when we make corrections, we say we make corrections, we label the corrections, and we explain why we did so. As opposed to, say, a completely user-generated encyclopedia of the world which people everywhere are treating as the gospel, even though contributions to the thing are like so much concentrated graffiti on an unpainted wall.
I know some people like to cast suspicion - perhaps it's fun, perhaps there's a motive, most likely there isn't. In the world of print, when you don't like a magazine, you register your displeasure by not reading and not subscribing. When readers of a magazine feel they don't like what they read, they may choose to put the item down unless something in their mind tells them there's a good reason not to. If a few readers of BetaNews feel a little suspicious, but they keep coming back and coming back again, then one way or the other, we must be doing the right thing, and whether or not they feel it, they know it. Which may be why you see the same names casting the same suspicions.
-SF3
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|What is
"But surprisingly, an Intel spokesperson downplayed the rumors by effectively confirming that Intel would not integrate memory controllers into its Penryn CPUs -- the first generation of 45nm architecture. Intel then went on to explain why such integration may be a bad design choice, using AMD -- which has used integrated HyperTransport since before the dual-core era - as a negative example."
If not using HyperTransport and an integrated memory controller interchangeably as the same thing?
If it isn't, then what is integrated HyperTransport? How can the processors data link/bus not be integrated? :/
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|Hypertransport is AMD's "terminology" and method to their integrated memory controller. Is HyperTransport and integrated memory controller the same? Not really, but since thus far, the only intg. memory controllers currently use hypertransport, people like Scott use those terms interchangeably. I know I have--now, I'll have to change my terminology from Hypertransport to the general "integrated memory controller" since HyperTransport is no longer the only implementation it seems.
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|This is all very strange. I've believed since getting an Opteron in 2003 that HyperTransport was a data bus - a replacement (and then some) to Intel's front side bus.
AMD was even talking about using HyperTransport linked sockets in the motherboard for plug in coprocessors. What's going on?
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|I see what's going on now. You are right; HyperTransport is a data bus. There is technology that attaches to being able to integrate that direct link to memory that HyperTransport enables, and that's where the integrated memory controllers come in.
Now that I see where the confusion is coming from, I'll be more careful in distinguishing these terms from one another. Here's how it should be:
Direct Connect Architecture is AMD's overall system for bussing memory directly to the CPU.
HyperTransport is the bus which accomplishes this.
Memory controllers are embedded into the CPU that serve as bus adapters.
http://developer.amd.com/article_print.jsp?id=8
-SF3
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|{accidental double post}
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|Drat! No ignore button... :D
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|Why don't you leave then? Oh yeah, because you're a troll.
/ignore
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|*chuckles*
It is a little amusing to watch Intel back-pedal like this - first saying HTT was an inferior technology, and now implementing it on their own chips in the future. If it wasn't for the startling performance of Conroe, I'd say Intel was playing catch-up, yet again. :)
(edited for clarity, thanks Tene)
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|HT in that context is HyperThreading, which was first included on some of the Pentium 4 Northwood Cs, in 2003.
Yes, I'm confused by the article's author, too.
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