Why PCI Express 2.0 Could Drive Down OEM Costs

Yesterday, with a minimum of fanfare, the member organizations of the PCI Special Interest Group (PCI-SIG) ratified its 2.0 draft for the PCI Express bus standard. On the surface, it seems the vote marks a victory for speed, with the interconnection rate on the bus doubling to 5 billion transfers per second. But just that fact alone could trigger a generational shift in motherboards, the end result of which could be tremendously reduced costs, and more rapid "mainstreaming" of current top-of-the-line features.

Understanding why this could be so takes you on a virtual road trip through the global information economy.

Chipsets on modern PCs are typically application-specific integrated circuits (ASICs) - logic devices that are programmed at the factory. In the broader information industry, entire systems-on-a-chip (SoC), complete with processors, controllers, and memory, are all programmed onto a single ASIC. While the cost of setting up the factory processes and tooling just to produce a single ASIC can be relatively expensive, the costs are generally recouped through mass production that improves profit margin.

As designers of embedded systems know very well, field-programmable gate arrays (FPGAs) can dramatically reduce implementation costs - setting up on-board logic is a lot more like "flashing" than manufacturing. But up until now, the bus upon which an FPGA-driven system has relied has been PCIe 1.1, whose transfer speeds were limited to 2.5 GT/s.

Doubling this speed with PCIe 2.0 makes the use of FPGAs in embedded system designs more attractive to the PCI-SIG's next target market: telecom equipment manufacturers. While members Intel, AMD, and nVidia all have designs on producing the first desktop and notebook PC implementations for early adopters, even that's not as lucrative a market for the group as the telecom industry whose leaders, as BetaNews noted last week, are in a race with one another to upgrade their wireless networks for mobile broadband support.

Telecom equipment is designed around an interconnect standard called AdvancedTCA, or ATCA. With a 5 GT/s maximum, FPGA designers such as Xilinx can build bridges between higher-speed communications equipment and embedded SoCs using PCIe 2.0 to serve as a bridge. This will compel the telecom companies to make major investments in FPGA to help speed their transition, as well as reduce their costs.

That investment, the PCI-SIG predicts, will take place extremely rapidly - practically from zero to warp speed in just the first half of this year.

One of the major cost-reduction drivers has to do with the nature of FPGA board design itself. PCI Express is all about removing clock synchronization from the equation - one less expensive component to worry about. Instead, the clock signal is embedded in the serial connection, using a process called clock data recovery, in which the "beat" at which a signal is paced is recovered by the receiving end, which actually listens for it. Embedding the clock in the signal dramatically simplifies system design; but what's more, it drives up industry's investment in the tools needed for them to implement that simplification.

With telecom leading the way, PC makers - who can't afford this year to race on "full rich," as it were - can comfortably draft just behind it. Once telecom makes its big investment (it almost can't afford not to), the costs of retooling for implementing FPGA in mainstream PC designs could be reduced significantly. By the latter half of this year, we could see new ideas for mass-produced PCs that use lower-cost logic, communicate more rapidly with 2007's graphics cards, and still use less power.

But PC builders no longer constitute the largest or even most significant recipient of this technological benefit; instead, according to rational predictions, they'll be the "trickle down" recipients of cost-reducing technologies being pushed more toward the telecom industry. Still, there's one payoff in PCIe 2.0 reserved for the PC realm exclusively: a feature called input/output virtualization.

Once implemented in new systems this year and into 2008, this will enable virtual PCs (using Microsoft Virtual PC or Virtual Server, or VMware) to communicate directly with physical components on the PCIe 2.0 bus. This could mean a virtual Windows Vista installation will be able to recognize the 3D processor on your physical graphics card, and use it to produce the full Aero front end rather than rely on its own cheap, fake graphics card.

So when you're exploring a 3D world on a virtual PC, perhaps sometime later this year, you might have WiMAX and HSDPA proponents to thank.